1. Field of the Invention
The invention relates to a memory module and to a memory controller for controlling a memory module. Further, the invention relates to method for controlling a memory module having a plurality of memory chips and a plurality of connections.
2. Description of Related Art
Memory or computer memory, e.g. based on DRAM technology, can be built in the form of Dual Inline Memory Modules (DIMM). Such a DIMM includes a number of memory chips on a printed circuit board and is plugged into the main board of the computer. The number of connections or connector contacts from the DIMM to the main board is limited by mechanical and reliability issues.
Over time, the memory capacity has grown. A conventional DIMM containing 1 GB of memory has 64 bidirectional data connections, 14 multiplexed address connections and additional connections for clock, status, power and the like. For other markets, such as servers, the format and connector assignments can be different. Since the market for memory is very large, changing the format, including the mechanical dimensions, connector density or type, can be difficult.
Depending on a current application, a computer needs to access memory in different granularity. While some applications read and write entire cash lines of 64 bytes or 128 bytes, other applications can need less data from each address.
However, the pin-out of conventional DIMM fixes the ratio of address transfers and data transfers and hence the optimal granularity. If data is accessed with lower granularity, the data throughput will decrease, because the access rate is limited by the address wires.
U.S. Pat. No. 2010/0036997 A1, a multiple data channel memory module architecture is described. U.S. Pat. No. 2010/0262790 A1 shows memory controllers, methods, and systems supporting multiple memory modes. In U.S. Pat. No. 2010/0293325 A1, memory devices and systems including multi-speed access of memory modules are described. Reference U.S. Pat. No. 6,705,877 B1 shows stackable memory module with variable bandwidth. In U.S. Pat. No. 7,739,441 B1, communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol is described
M. Awasthi et al. “Handling the problems and opportunities posed by multiple on-chip memory controllers”, PACT'10, Vienna, Austria, ACM 978-1-4503-0178-7/10/09 mentions a solution for handling the problems and opportunities posed by multiple on-chip memory controllers. In F. Cabarcas et al. “Interleaving granularity on high bandwidth memory architecture for CMPs”, IEEE, 978-1-4244-7938-2/10 interleaving granularity on high bandwidth memory architecture for CMPs is described.
Accordingly, it is an aspect of the present invention to provide a memory module with a configurable ratio of address transfers and data transfers.